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d a t a sh eet product speci?cation supersedes data of 2003 jun 20 2004 mar 22 integrated circuits 74lvc574a octal d-type flip-flop with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state
2004 mar 22 2 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a features 5 v tolerant inputs and outputs, for interfacing with 5 v logic supply voltage range from 1.2 to 3.6 v inputs accept voltages up to 5.5 v cmos low power consumption direct interface with ttl levels high impedance when v cc =0v 8-bit positive edge-triggered register independent register and 3-state buffer operation flow-through pin-out architecture complies with jedec standard no. 8-1a esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. specified from - 40 to +85 c and - 40 to +125 c. description the 74lvc574a is a high-performance, low-power, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3 or 5 v devices. in 3-state operation, outputs can handle 5 v. this feature allows the use of these devices as translators in a mixed 3.3 and 5 v environment. the 74lvc574a is an octal d-type flip-flop featuring separate d-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. a clock (cp) and an output enable ( oe) input are common to all flip-flops. the eight flip-flops will store the state of their individual d-inputs that meet the set-up and hold times requirements on the low-to-high cp transition. when oe is low, the contents of the eight flip-flops is available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the flip-flops. the 74lvc574a is functionally identical to the 74lvc374a, but has a different pin arrangement. quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . symbol parameter conditions typical unit t phl /t plh propagation delay cp to qn c l = 50 pf; v cc = 3.3 v 3.2 ns f max maximum clock frequency 150 mhz c i input capacitance 5.0 pf c pd power dissipation capacitance per ?ip-?op notes 1 and 2 15 pf
2004 mar 22 3 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a function table see note 1. note 1. h = high voltage level; h = high voltage level one set-up time prior to the low-to-high cp transition; l = low voltage level; l = low voltage level one set-up time prior to the low-to-high cp transition; - = low-to-high clock transition; z = high-impedance off-state. ordering information operating mode input internal flip-flop output oe cp dn qn load and read register l - lll l - hhh load register and disable outputs h - llz h - hhz type number package temperature range pins package material code 74lvc574ad - 40 to +125 c 20 so20 plastic sot163-1 74lvc574adb - 40 to +125 c 20 ssop20 plastic sot339-1 74lvc574apw - 40 to +125 c 20 tssop20 plastic sot360-1 74LVC574ABQ - 40 to +125 c 20 dhvqfn20 plastic sot764-1 pinning pin symbol description 1 oe output enable input (active low) 2 d0 data input 3 d1 data input 4 d2 data input 5 d3 data input 6 d4 data input 7 d5 data input 8 d6 data input 9 d7 data input 10 gnd ground (0 v) 11 cp clock input (low-to-high; edge triggered) 12 q7 data output 13 q6 data output 14 q5 data output 15 q4 data output 16 q3 data output 17 q2 data output 18 q1 data output 19 q0 data output 20 v cc supply voltage pin symbol description
2004 mar 22 4 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a handbook, halfpage oe d0 d1 d2 d3 574 d4 d5 d6 d7 gnd v cc q0 q1 q2 q4 q5 q3 q6 q7 cp 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 mna797 fig.1 pin configuration so20 and (t)ssop20. handbook, halfpage 1 2 3 4 5 6 7 8 9 d0 d1 d2 d3 d4 d5 d6 d7 19 18 17 16 15 14 13 12 q1 q0 q2 q3 q4 q5 q6 q7 20 oe v cc 10 11 gnd top view cp gnd (1) mna978 fig.2 pin configuration dhvqfn20. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. handbook, halfpage mna798 d0 d1 d2 d3 d4 d5 d6 d7 oe cp q0 q1 q2 q3 q4 q5 q6 q7 11 1 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 fig.3 logic symbol. handbook, halfpage mna799 12 13 14 15 16 17 18 1 c1 11 en 1d 19 9 8 7 6 5 4 3 2 fig.4 logic symbol (ieee/iec).
2004 mar 22 5 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a handbook, halfpage mna800 3-state outputs ff1 to ff8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 cp oe 9 11 1 8 7 6 5 4 3 2 fig.5 functional diagram. handbook, full pagewidth mna801 q4 d4 q3 d3 q2 d2 q1 d1 q0 d0 d ff1 q cp cp d ff2 q cp d ff3 q cp d ff4 q cp d ff5 q cp d ff6 q cp d ff7 q cp d ff8 q cp oe q5 d5 q6 d6 q 7 d7 fig.6 logic diagram.
2004 mar 22 6 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so20 packages: above 70 c the value of p tot derates linearly with 8 mw/k. for (t)ssop20 packages: above 60 c the value of p tot derates linearly with 5.5 mw/k. for dhvqfn20 packages: above 60 c the value of p tot derates linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low-voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage output high or low state 0 v cc v output 3-state 0 5.5 v t amb operating ambient temperature in free air - 40 +125 c t r , t f input rise and fall times v cc = 1.2 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0 -- 50 ma v i input voltage note 1 - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage output high or low state; note 1 - 0.5 v cc + 0.5 v output 3-state; note 1 - 0.5 +6.5 v i o output source or sink current v o =0tov cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 to +125 c; note 2 - 500 mw
2004 mar 22 7 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a dc characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb = - 40 to +85 c; note 1 v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 12 ma 2.7 v cc - 0.5 -- v i o = - 100 m a 3.0 v cc - 0.2 v cc - v i o = - 18 ma 3.0 v cc - 0.6 -- v i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il i o =12ma 2.7 -- 0.40 v i o = 100 m a 3.0 - gnd 0.20 v i o =24ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd; note 2 3.6 - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd 3.6 - 0.1 10 m a i off power-off leakage supply v i or v o = 5.5 v 0.0 - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 - 0.1 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0 2.7 to 3.6 - 5 500 m a
2004 mar 22 8 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a notes 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. 2. the specified overdrive current at the data input forces the data input to the opposite logic input state. t amb = - 40 to +125 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 12 ma 2.7 v cc - 0.65 -- v i o = - 100 m a 2.7 to 3.6 v cc - 0.3 -- v i o = - 18 ma 3.0 v cc - 0.75 -- v i o = - 24 ma 3.0 v cc - 1 -- v v ol low-level output voltage v i =v ih or v il i o =12ma 2.7 -- 0.6 v i o = 100 m a 2.7 to 3.6 -- 0.3 v i o =24ma 3.0 -- 0.8 v i li input leakage current v i = 5.5 v or gnd 3.6 -- 20 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd 3.6 -- 20 m a i off power-off leakage supply v i or v o = 5.5 v 0.0 -- 20 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0 2.7 to 3.6 -- 5000 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2004 mar 22 9 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a ac characteristics gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . notes 1. all typical values are measured at t amb =25 c. 2. these typical values are measured at v cc = 3.3 v. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c; note 1 t phl /t plh propagation delay cp to qn see figs 7 and 10 2.7 1.5 3.6 8.0 ns 3.0 to 3.6 1.5 3.2 (2) 7.0 ns t pzh /t pzl 3-state output enable time oe to qn see figs 9 and 10 2.7 1.5 4.3 8.5 ns 3.0 to 3.6 1.5 3.5 (2) 7.5 ns t phz /t plz 3-state output disable time oe to qn see figs 9 and 10 2.7 1.5 2.8 6.5 ns 3.0 to 3.6 1.5 2.5 (2) 6.0 ns t w clock pulse width high or low see fig.7 2.7 3.3 -- ns 3.0 to 3.6 3.4 1.7 (2) - ns t su set-up time dn to cp see fig.8 2.7 2.0 -- ns 3.0 to 3.6 2.0 0.3 (2) - ns t h hold time dn to cp see fig.8 2.7 1.5 -- ns 3.0 to 3.6 1.5 - 0.2 (2) - ns f max maximum clock frequency 2.7 80 -- mhz 3.0 to 3.6 100 150 (2) - mhz t sk(0) skew note 3 3.0 to 3.6 -- 1.0 ns t amb = - 40 to +125 c t phl /t plh propagation delay cp to qn see figs 7 and 10 2.7 -- 10.0 ns 3.0 to 3.6 -- 9.0 ns t pzh /t pzl 3-state output enable time oe to qn see figs 9 and 10 2.7 -- 11.0 ns 3.0 to 3.6 -- 9.5 ns t phz /t plz 3-state output disable time oe to qn see figs 9 and 10 2.7 -- 8.5 ns 3.0 to 3.6 -- 7.5 ns t w clock pulse width high or low see fig.7 2.7 --- ns 3.0 to 3.6 --- ns t su set-up time dn to cp see fig.8 2.7 --- ns 3.0 to 3.6 --- ns t h hold time dn to cp see fig.8 2.7 --- ns 3.0 to 3.6 --- ns f max maximum clock frequency 2.7 --- mhz 3.0 to 3.6 --- mhz t sk(0) skew note 3 3.0 to 3.6 --- ns
2004 mar 22 10 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a ac waveforms handbook, full pagewidth mna802 cp input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m fig.7 clock (cp) to output (qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. handbook, full pagewidth mna803 gnd gnd t h t su t h t su v m v m v m v i v oh v ol v i qn output cp input dn input fig.8 data setup and hold times for the dn input to the cp input. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. the shaded areas indicate when the input is permitted to change for predictable output performance.
2004 mar 22 11 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a handbook, full pagewidth mna804 t plz t phz outputs disabled outputs enabled v y v x outputs enabled q n output low-to-off off-to-low q n output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m fig.9 3-state enable and disable times. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. v x =v ol + 0.3 v at v cc 3 2.7 v; v x =v ol + 0.1v cc at v cc < 2.7 v. v y =v oh - 0.3 v at v cc 3 2.7 v; v y =v oh - 0.1v cc at v cc < 2.7 v. handbook, full pagewidth open gnd 2 v cc v cc v i v o mna815 d.u.t. c l = 50 pf r t r l = 500 w r l = 500 w pulse generator s1 fig.10 load circuitry for switching times. test s1 t plh /t phl open t plz /t pzl 2 v cc t phz /t pzh gnd v cc v i <2.7 v v cc 2.7 to 3.6 v 2.7 v definitions for test circuit: r l = load resistor. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to z o of pulse generators.
2004 mar 22 12 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
2004 mar 22 13 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p q (1) z y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o o 0.13 1.25 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot339-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 110 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 a max. 2
2004 mar 22 14 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
2004 mar 22 15 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2004 mar 22 16 philips semiconductors product speci?cation octal d-type ?ip-?op with 5 v tolerant inputs/outputs; positive edge-trigger; 3-state 74lvc574a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r20/03/pp 17 date of release: 2004 mar 22 document order number: 9397 750 13028

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